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fn6612 rev 0.00 page 1 of 13 december 21, 2007 fn6612 rev 0.00 december 21, 2007 isl9107, isl9108 1.5a 1.6mhz low quiescent current high efficiency synchronous b uck regulator datasheet isl9107 and isl9108 are 1.6m hz synchronous step-down regulators with integrated power switches capable of delivering 1.5a output current, which is ideal for powering low-voltage microprocessors in compact devices such as pdas and cellular phones. thes e devices are optimized for generating low output voltages down to 0.8v. the supply voltage range is from 2.7v to 5. 5v allowing for the use of a single li+ cell, three nimh cells or a regulated 5v input. 1.6mhz pulse-width modulati on (pwm) switching frequency allows using small external components. they have flexible operation mode selection of f orced pwm mode and skip (low i q ) mode with typical 17 ? a quiescent current for highest light load efficiency to maximize battery life. the isl9107 and isl9108 integrate a pair of low on-resistance p-channel and n-channel mosfets to maximize efficiency and mi nimize external component count. the isl9107 offers a typical 215ms power-good (pg) timer when powered up. the timer output can be reset by rsi. when shutdown, isl9107 and isl9108 discharge the output capacitor. other featu res include internal digital soft-start, enable for power sequence, ove rcurrent protection, and thermal shutdown. the isl9107 and isl9108 are offered in 8 ld 2mmx3mm dfn package with 0.9mm typi cal height. the complete converter can occupy less than 1cm 2 area. features ? integrated synchronous buck regulator with up to 95% efficiency ? 2.7v to 5.5v supply voltage ? 1.5a guaranteed output current ?17 ? a quiescent supply current in skip (low i q ) mode ? selectable forced pwm mode and skip mode ? less than 1a logic controlled shutdown current ? 100% maximum duty cycle for lowest dropout ? discharge output capacitor when shutdown ? internal digital soft-start ? enable, peak current limiting, short circuit protection ? over-temperat ure protection ? power-good functio n (for isl9107 only) ? 8 ld 2mmx3mm dfn ? pb-free (rohs compliant) applications ? single li-ion battery-powered equipment ? dsp core power ? pdas and palmtops pinouts isl9107 (8 ld 2x3 dfn) top view isl9108 (8 ld 2x3 dfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL9107IRZ-T 107 -40 to +85 8 ld 2x3 dfn l8.2x3 isl9108irz-t 108 -40 to +85 8 ld 2x3 dfn l8.2x3 *please refer to tb347 for det ails on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material set s; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb a nd pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020. 2 3 4 1 7 6 5 8 vin en pg mode sw gnd fb rsi sw gnd fb nc vin en nc mode 2 3 4 1 7 6 5 8
isl9107, isl9108 fn6612 rev 0.00 page 2 of 13 december 21, 2007 absolute maximum ratings (reference to gnd) thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v en, mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v pg, rsi (note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v sw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.5a ambient temperature range . . . . . . . . . . . . . . . . . . .- 40c to +85c thermal resistance (notes 2, 3) ? ja (c/w) ? jc (c/w) 2x3 dfn package . . . . . . . . . . . . . . 78 11 junction temperature range. . . . . . . . . . . . . . . . . .-4 0c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-6 5c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. for isl9107 only. 2. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 3. ? jc , case temperature location is at the center of the exposed m etal pad on the package underside. see tech brief tb379. electrical specifications unless otherwise noted, all parameter limits are guaranteed ove r the recommended operating conditions and the typical specifications are m easured at the following condit ions: t a = +25c, v in = v en = 3.6v, l = 2.2h, c 1 = 10f, c 2 = 10f, i out = 0a (see the typical appl ication circuit on page 7). parameter symbol test conditions min typ max units supply undervoltage lockout threshold v uvlo rising - 2.5 2.7 v falling 2.2 2.4 - v quiescent supply current i vin mode = v in , no load at the output - 17 30 a mode = gnd, no load at the output - 5 8 ma shut down supply current i sd v in = 5.5v, en = low - 0.05 2 ? a output regulation fb regulation voltage v fb t a = 0c to +85c 0.784 0.8 0.816 v t a = -40c to +85c 0.78 0.8 0.82 v fb bias current i fb vfb = 0.75v - 0.1 - a line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) - 0.2 - %/v compensation error amplifier trans-conductanc e design info only - 20 - a/v sw p-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.12 0.22 ? v in = 2.7v, i o = 200ma - 0.16 0.27 ? n-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.11 0.22 ? v in = 2.7v, i o = 200ma - 0.15 0.27 ? n-channel bleeding mosfet on-resistance - 90 - ? p-channel mosfet peak current limit i pk v in = 5.5v 1.8 2.1 2.6 a maximum duty cycle - 100 - % pwm switching frequency f s t a = -40c to +85c 1.35 1.6 1.75 mhz sw minimum on-time mode = l ow (forced pwm mode) - - 100 ns soft start-up time -1.1- ms
isl9107, isl9108 fn6612 rev 0.00 page 3 of 13 december 21, 2007 pg (note 1) output low voltage sinking 1ma, vfb = 0.7v - - 0.3 v delay time 150 215 275 ms pg pin leakage current pg = v in = 3.6v - 0.01 0.1 a minimum supply voltage for valid pg signal 1.2 - - v internal pgood low rising thres hold percentage of nominal regula tion voltage 89.5 92 94.5 % internal pgood low falling threshold percentage of nominal regul ation voltage 85 88 91 % internal pgood high rising threshold percentage of nominal regul ation voltage 108.2 110.7 113.2 % internal pgood high falling thre shold percentage of nominal regu lation voltage 104 107 110 % internal pgood delay time -50- s rsi (note 1), en, mode logic input low --0.4v logic input high 1.4 - - v logic input leakage current pulled up to 5.5v - 0.1 1 a thermal shutdown - 150 - c thermal shutdown hysteresis -25-c electrical specifications unless otherwise noted, all parameter limits are guaranteed ove r the recommended operating conditions and the typical specifications are m easured at the following condit ions: t a = +25c, v in = v en = 3.6v, l = 2.2h, c 1 = 10f, c 2 = 10f, i out = 0a (see the typical appl ication circuit on page 7). (continued) parameter symbol test conditions min typ max units pin descriptions pin # isl9107 pin name isl9108 pin name description 1vin input supply voltage pin. connect a 10f ceramic capacitor to p ower ground . 2 en enable pin. enable the output when driven to high. shut down the chip and discharge output capacitor when driven to low. do not leave this pin floating. 4 mode mode selection pin. connect to logic high or vin to enable skip mode; connect to logic low or ground for force pwm mode. 6 fb buck regulator output feedback pin. connect to the output vo ltage through voltage divider resistors for adjustable output voltage. 7 gnd system ground. 8 sw switching node pin. connect to one terminal of the inductor. e-pad - exposed pad. it should be connected to ground for proper electrical performance. the exposed pad must also be connected to as much as possible for optimal thermal perform ance. 3 pg nc for isl9107, it is 215ms timer output. it outputs 215ms de layed power-good signal when output voltage is within power-good window. it can be reset by a high rsi signal, then 215ms starts when rsi goes from high to low. for isl9108, do not connect. leave this pin floating. 5 rsi nc for isl9107, this input res ets the 215ms timer. please re fer to theory of operation on page 9 for more details. for isl9108, do not connect. leave this pin floating.
isl9107, isl9108 fn6612 rev 0.00 page 4 of 13 december 21, 2007 typical operating performance figure 1. efficieny vs load current (v out = 3.3v) figure 2. efficiency vs load current (v out = 2.5v) figure 3. efficiency vs load current (v out = 1.6v) figure 4. i q vs v in (mode = v in , v out = 1.6v, i out = 0) figure 5. i q vs v in (mode = gnd, v out = 1.6v, i out = 0) 50 55 60 65 70 75 80 85 90 95 100 0 500 1000 1500 load current (ma) efficiency (%) v in = 3.6v v in = 4.2v 0 500 1000 1500 50 55 60 65 70 75 80 85 90 95 100 load current (ma) efficiency (%) v in = 4.2v v in = 3.6v 50 55 60 65 70 75 80 85 90 95 100 0 500 1000 1500 load current (ma) efficiency (%) efficiency @ 2.7v efficiency @ 3.6v efficiency @ 4.2v 0 5 10 15 20 25 30 2.7 3.4 4.1 4.8 5.5 input voltage (v) quiescent current (a) 0 1 2 3 4 5 6 7 8 2.7 3.4 4.1 4.8 5.5 input voltage (v) quiescent current (ma)
isl9107, isl9108 fn6612 rev 0.00 page 5 of 13 december 21, 2007 figure 6. soft-start (v in = 4.2v, v out = 1.6v, i out =1.5a) figure 7. soft-start (v in = 4.2v, v out = 1.6v, i out =1ma) figure 8. steady-state in skip mode (v in = 5.0v, v out = 1.6v, i out = 35ma) figure 9. steady-state in pwm mode (v in = 5.0v, v out = 1.6v, i out = 1.5a) figure 10. load transient test (mode = v in = 5.0v; v o = 1.6v; i o = 0.01a~1a) figure 11. load transient test (mode = gnd, v in = 5.0v; v o = 1.6v; i o = 0.01a~1a) typical operating performance (continued) 5v/div 1v/div 5v/div 1a/div 200s/div v sw v out i l en 200s/div 5v/div 1v/div 5v/div 500ma/div v sw v out i l en 2s/div 200ma/div 5v/div v out (ac coupled) v sw 50mv/div i l 1s/div 1a/div 20mv/div 5v/div v out (ac coupled) v sw i l 100s/div 1a/div 100mv/div 5v/div v out (ac coupled) v sw i l 100s/div 1a/div 100mv/div 5v/div v out (ac coupled) v sw i l v sw
isl9107, isl9108 fn6612 rev 0.00 page 6 of 13 december 21, 2007 figure 12. load transient test (mode = v in = 4.2v; v o = 1.6v; i o = 0.01a~1a) figure 13. load transient test (mode = gnd, v in = 4.2v; v o = 1.6v; i o = 0.01a~1a) figure 14. load transient test (mode = v in = 3.6v; v o = 1.6v; i o = 0.01a~1a) figure 15. load transient test (mode = gnd, v in = 3.6v; v o = 1.6v; i o = 0.01a~1a) typical operating performance (continued) 100s/div 1a/div 100mv/div 5v/div v out (ac coupled) v sw i l 100s/div 1a/div 100mv/div 5v/div v out (ac coupled) v sw i l 100s/div 1a/div 100mv/div 5v/div v out (ac coupled) v sw i l 100s/div 1a/div 100mv/div 5v/div v out (ac coupled) v sw i l
isl9107, isl9108 fn6612 rev 0.00 page 7 of 13 december 21, 2007 typical applications figure 16. typical application diagram for isl9107 and isl9108 parts description manufacturers pa rt number specifications size l inductor sumida cdrh4d15/snp-2r2nc 2.2h/2.0a/48m ? 4.4mmx4.4mmx1.7mm c1 input capacitor murata grm21br60j106ke19l 10f/6.3v 2.0mmx1.25m mx1.25mm c2 output capacitor murata grm21br60j106ke19l 10f/6.3v 2.0mmx1.2 5mmx1.25mm c3 capacitor murata grm188r71h221ka01c 220pf/50v 1.6mmx0.8mmx0.8mm r1(isl9107) resistor various 100k ?? smd, ?? 1.6mmx0.8mmx0.45mm r2, r3 resistor various 100k ?? smd, ?? 1.6mmx0.8mmx0.45mm isl9107 sw gnd fb rsi vin en pg mode input output 1.6v/0a~1.5a r1 100k r2 100k r3 100k 2.7v to 5.5v e-pad c2 10f l 2.2h c3 220pf c1 10f isl9108 sw gnd fb nc vin en mode nc input output 1.6v/0a~1.5a r2 100k r3 100k 2.7v to 5.5v e-pad c2 10f l 2.2h c3 220pf c1 10f
isl9107, isl9108 fn6612 rev 0.00 page 8 of 13 december 21, 2007 block diagram figure 17. functional block diagram *note: only applies to isl9107. sw + + csa + + ocp vref1 skip + + soft- start 0.8v eamp comp pwm/pfm logic controller protection driver fb + pg* mode shutdown vin gnd + bandgap scp + en shutdown rsi* vref2 vref3 vref4 vref5 zero-cross sensing slope comp pgood delay oscillator + *note
isl9107, isl9108 fn6612 rev 0.00 page 9 of 13 december 21, 2007 theory of operation the isl9107 and isl9108 are ste p-down switching regulators optimized for battery-power ed handheld applications. the regulators operate at typical 1.6mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, t he regulators can be se lected to enter sk ip mode to reduce the switching fr equency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the quiescent current under skip mode with no loading is typically only 17a. the supply current is typically only 0.1a when the regulator is disabled. pwm control scheme these devices use the peak -current-mode pulse-width modulation (pwm) cont rol scheme for fast transient response and pulse-by-pulse current limiting. figure 17 shows the circui t functional block diagram. the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit and the slope compensation for the current loop stability. the current sensing circuit consist s of the resistance of the p- channel mosfet when it is tur ned on and the current sense amplifier (csa). the control reference fo r the current loops comes from the error amplifier (eamp) of the voltage loop. the pwm operation is initial ized by the clock from the oscillator. the p-channel m osfet is turned on at the beginning of a pwm cycle and th e current in the p-channel mosfet starts ramping up. wh en the sum of the csa output and the compensation slope reac hes the control reference of the current loop, th e pwm comparator c omp sends a signal to the pwm logic to turn off the p-channel mosfet and to turn on the n-channel mosfet. the n-mosfet remains on till the end of the pwm cycle. figure 18 shows the typical operating waveforms during the normal pw m operation. the dotted lines illustrate the sum of the slope compensation ramp and the csa output. the output voltage is regulated by controlling the reference voltage to the current loop. t he bandgap circuit outputs a 0.8v reference voltage to the voltag e control loop. the feedback signal comes from the fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately in soft start-up on page 10. the eamp is a transconductance amplifier, whi ch converts the voltage error signal to a current output. the voltage loop is internally compensated by a rc network . the maximum eamp voltage output is precisely clam ped to the bandgap voltage. skip mode with the mode pin connected to logic high, the device enters a pulse-skipping mode at light lo ad to minimize the switching loss by reducing the switching frequency. figure 19 illustrates the skip mode operatio n. a zero-cross sensing circuit (as shown in figure 17) monitors the n-channel mosfet current for zero crossing. when it is detected to cross zero for 8 consecutive cycles, the regulato r enters the skip mode. during the 8 consecutive cycles, the inductor current could be negative. the counter is rese t to zero when the sensed n- channel mosfet current doe s not cross zero during any cycle within the 8 consecutive cyc les. once the device enters the skip mode, the pulse modulatio n starts being controlled by the skip comparator shown in f igure 17. each pulse cycle is still synchronized by the pwm clock. the p-channel mosfet is turned on at the rising edge of clock and turned off when it s current reaches 20% of the peak current lim it. as the average inductor current in e ach cycle is higher than the average current of the load, the output v oltage rises cycle over cycle. when the output voltage reac hes 1.5% above its nominal voltage, the p-channel mosfet is turned off immediately and the inductor current is fully d ischarged to zero and stays at zero. the output voltage reduce s gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal vol tage, the p-ch annel mosfet will be turned on agai n, repeating the pr evious operations. the regulator resumes normal pwm mode operation when the output voltage is sensed to dr op below 1.5% of its nominal voltage value. enable the enable (en) pin allows the user to enable or disable the converter for purposes such as power-up sequencing. with the en pin pulled to high, the converter is enabled, the internal reference circuit wakes up first and then the soft start-up begins. when the en pin is pulled to logic low, the converter i s disabled, the p-channel mosfe t is turned off immediately and the output capacitor is discharged through internal discharge path. undervoltage lockout (uvlo) when the input voltage is bel ow the undervoltage lockout (uvlo) threshold, the device is disabled. figure 18. pwm operation waveforms v eamp d i l v out v csa
isl9107, isl9108 fn6612 rev 0.00 page 10 of 13 december 21, 2007 mode selection the mode pin is provided on i sl9107 and isl9108 to select the operation mode. whe n it is driven to lo gic low or ground, the regulator operates in fo rced pwm mode. under forced pwm mode, the device remains at the fixed pwm operation (typical at 1.6mhz), regardless of if the load current is high or low. when the mode pin is driven to logic hig h or connected to input voltage v in , the regulator operates in either skip mode or fixed pwm mode depending on t he different load conditions. overcurrent protection the overcurrent protection is provided when an overload condition happens. it is realized by monitoring the csa output with the ocp comparator, as s hown in figure 17. when the current at p-channel mosfet is sensed to reach the current limit, the ocp comparator is triggered to turn off the p-channe l mosfet immediately. short-circuit protection as shown in figure 17, the device has a short-circuit protectio n (scp) comparator, which monit ors the fb pin voltage for output short-circuit protection . when the fb voltage is lower than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to 1/3 of it s normal operation frequency. soft start-up the soft start-up eliminates the inrush current during the circ uit start-up. the soft-start block out puts a ramp reference to both the voltage loop and the current l oop. the two ram ps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the star t-up, the output voltage is le ss than 0.2v; hence the pwm opera ting frequency is 1/3 of the normal frequency. power mosfets the power mosfets are optimized to achieve better efficiency. the on-resistance for the p-channel mosfet is typically 0.16 ? and the typical on-resistance for the n-channel mosfet is 0.15 ? . low dropout operation the isl9107 and isl9108 featur e low dropout o peration to maximize the battery life. when the input voltage drops to a level that the device can no longer opera te under switching regulation to maintain the output voltage, the p-channel mosfet is complete ly turned on (100% duty cycle). the dropout voltage under such condition is the product of the load current and the on-resistance of the p-channel mosfet. minimum required input voltage v in under this condition is the sum of the output voltage plu s the voltage drop cross the inductor and the p-c hannel mosfet switch. thermal shut down the isl9107 and isl9108 provide a built-in thermal protection function. the therma l shutdown threshold temperature is typical +160c with typical +25 c hysteresis. when the internal temperature is sensed to reac h +150c, the regulator is completely shut down and as t he temperature is sensed to drop to +125c (typical), the device resumes operation starting from the soft start-up. rsi signal the rsi signal is an input signal, which can reset the pg signal. as shown in figure 17, t he power-good signal is gated by the rsi signal. when the rsi is high, the pg signal remains low, regardless of the output volt age condition. this function is provided on isl9107 only. power-good the isl9107 offers a power- good (pg) signal. when the output voltage is not within the power-good window, the pg pin outputs an open-drain low signal . when the output voltage is within the power-good window, an internal power-good signal is issued to turn off the open-drain mosfet so that the pg pin can be externally pulled to hig h. the rising edge of the pg output is delayed by 215ms (typi cal) from the time the power- good signal is issued. this func tion is provided on isl9107 only. figure 19. skip mode operation waveforms 8 cycles clock i l v out 0 v out_nominal 20% peak current limit 1.015*v out_nominal
isl9107, isl9108 fn6612 rev 0.00 page 11 of 13 december 21, 2007 applications information inductor and output capacitor selection to achieve better steady state and tr ansient response, typically a 2.2h inductor c an be used. the peak-to-peak inductor current ripple can be expressed as in equation 1: in equation 1, usually the typical values can be used but to have a more conservative estimation, the inductance should consider the value with wors t case tolerance; and for switching frequency (f s ), the minimum f s from the electrical specifications table on page 2 can be used. to select the inductor, its satur ation current rating should be at least higher than the sum of the maximum output current and half of the delta calculate d from equation 1. another more conservative approach is to select the inductor with the current rating higher than the p-channel mosfet peak current limit. another consideration is the inductor dc resistance since it directly affects the efficiency of the converter. ideally, the inductor with the lower dc re sistance should be considered to achieve highe r efficiency. inductor specifications could be different from different manufacturers so please check with each manufacturer if additional information is needed. for the output capacitor, a c eramic capacitor can be used because of the low esr values, which helps to minimize the output voltage ripple. a typical value of 10f/6.3v ceramic capacitor should be enough for most of the applications and the capacitor should be x5r or x7r. input capacitor selection the main function for the input capacitor is to provide decoupling of the parasitic induc tance and to provide filtering function to prevent the switching current from flowing back to the battery rail. a 10f/6.3v ce ramic capacitor (x5r or x7r) is a good starting point for t he input capacitor selection. output voltage setting resistor selection the voltage divi der resistors (r 2 and r 3 ), as shown in figure 16, set the desired output voltage value. the output voltage can be calculated using equation 2: where v fb is the feedback voltage (typically it is 0.8v). the current flowing through the volt age divider resistors can be calculated as v o /(r 2 + r 3 ), so larger resistance is desirable to minimize this current. on the other hand, the fb pin has leakage current that will cause error in the output voltage setting. the leakage current has a typical value of 0.1a. to minimize the accuracy impact o n the output voltage, select the r 3 no larger than 200k ? . c 3 (shown in figure 16) is highly recommended to be added for improving stability and achieving better transient response. c 3 can be calculated using equation 3: table 1 provides the recomme nded component values for some output voltage options. layout recommendation the pcb layout is a very important converter design step to make sure the designed convert er works well, especially under the high current, high sw itching frequency condition. for isl9107 and isl9108, the power loop is composed of the output inductor (l), the output capacitor (c out ), the sw pin and the gnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wid e; the same type of traces should be used to connect the vin pin, the input capacitor c in and its ground. the switching node of the converter, the sw pin, and the traces connec ted to this no de are very noisy, so keep the voltage f eedback trace and other noise sensitive traces away fr om these noisy traces. the input capacitor should be placed as close as possible to the vin pin. the gr ound of the input and output capacitors should be connected as c lose as possible as well. the heat of the i c is mainly dissipated through the thermal pad. maximizing the copper area connect ed to the thermal pad is preferable. in addition, a solid ground plane is helpful for emi performance. ? i v o 1 v o v in --------- C ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) v o v fb 1 r 2 r 3 ------ - + ?? ?? ?? ? = (eq. 2) table 1. isl9107 and isl9108 recommended circuit configuration vs v out v out (v) l (h) c 2 (f) r 2 (k ? )c 3 (pf) r 3 (k ?? 0.8 2.2 10 0 n/a 100 1.0 2.2 10 44.2 470 178 1.2 2.2 10 80.6 270 162 1.5 2.2 10 84.5 270 97.6 1.8 2.2 10 100 220 80.6 2.5 2.2~3.3 10~22 100 220 47.5 2.8 2.2~3.3 10~22 100 220 40.2 3.3 2.2~3.3 10~22 102 220 32.4 c 3 1 2 ? ? r 2 7.3khz ? ? ---------------------------------------------------- - = (eq. 3)
fn6612 rev 0.00 page 12 of 13 december 21, 2007 isl9107, isl9108 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2007. all rights reserved. all trademarks and registered trademarks are the property of their respective owners.
isl9107, isl9108 fn6612 rev 0.00 page 13 of 13 december 21, 2007 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3 8 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see in tersil technical brief tb389.

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